computer organization
c m s c 311  
f a l l   2 0 0 2  

Project #1

Due Friday, Dec. 13, 11:59 PM (just before midnight)
Late Due Date Sunday, Dec. 15, 11:59 PM (just before midnight)

Posted: November 27, 2002

Purpose

The goals of the project are:

Academic Integrity Statement

Please note that *all* programming projects in this course (including this one) are to be done independently or with the assistance of the instructional staff of this course only, unless otherwise specified IN PRINT by official webpages.

Please review the policies outlined on the class syllabus concerning the use of class computer accounts and concerning the University's Code of Academic Integrity. The instructors of this course will review the programs submitted by students for potential violations of the Code of Academic Integrity and if it is believed that a violation has occurred it will be referred to the Office of Judicial Programs and the Student Honor Council.

Hardcoding is considered a violation of academic integrity

Collaboration Policy

This project should be done invidividually. You may discuss ideas, but not exchange or view each other's code.

Specifications

You will be given a file called Translate.h and Load.h. The specifications are in the following link.

Translate Specification

Load Specification

Implement the methods. You may add helper methods, if you want.

Format of instructions

Note: || means concatentation
Note: 016 means 16 zeroes.
Note: PC refers to the program counter
Note:

Note:

Note: Bits are numbered so that B0 is the least signficant bit and B31 is the most significant bit.

Note: Minimum instructions needed to pass primary: add, addi, beq, j, jal, or, ori. You need to translate to and from.

Command Explanation
add $rd, $rs, $rt
  • Reg[ d ] = Reg[ s ] + Reg[ t ]
  • R-type instruction
  • B31-26 = 000000 (SPECIAL)
  • B10-6 = 000000
  • B5-0 = 100000 (ADD)
addi $rt, $rs, immed
  • Reg[ t ] = Reg[ s ] + (immed15)16 || immed15-0
  • I-type instruction
  • B31-26 = 001000
  • Immediate value is sign extended
sub $rd, $rs, $rt
  • Reg[ d ] = Reg[ s ] - Reg[ t ]
  • R-type instruction
  • B31-26 = 000000 (SPECIAL)
  • B10-6 = 000000
  • B5-0 = 100010 (SUB)
and $rd, $rs, $rt
  • Reg[ d ] = Reg[ s ] & Reg[ t ]
  • Bitwise AND
  • R-type instruction
  • B31-26 = 000000 (SPECIAL)
  • B10-6 = 000000
  • B5-0 = 100100 (AND)
andi $rt, $rs, immed
  • Reg[ t ] = Reg[ s ] & 016 || immed15-0
  • I-type instruction
  • B31-26 = 001100
  • Immediate value is zero extended
or $rd, $rs, $rt
  • Reg[ d ] = Reg[ s ] | Reg[ t ]
  • Bitwise OR
  • R-type instruction
  • B31-26 = 000000 (SPECIAL)
  • B10-6 = 000000
  • B5-0 = 100101 (OR)
ori $rt, $rs, immed
  • Reg[ t ] = Reg[ s ] | 016 || immed15-0
  • I-type instruction
  • B31-26 = 001101
  • Immediate value is zero extended
xor $rd, $rs, $rt
  • Reg[ d ] = Reg[ s ] ^ Reg[ t ]
  • Bitwise XOR
  • R-type instruction
  • B31-26 = 000000 (SPECIAL)
  • B10-6 = 000000
  • B5-0 = 100110 (XOR)
xori $rt, $rs, immed
  • Reg[ t ] = Reg[ s ] ^ 016 || immed15-0
  • I-type instruction
  • B31-26 = 001110
  • Immediate value is zero extended
beq $rs, $rt, LABEL
  • if ( Reg[ s ] == Reg[ t ] ) jump to LABEL else go to next instruction
  • I-type instruction
  • B31-26 = 000100
  • offset is B15-0
  • Jump to PC + [ (offset15)14 || offset || 02 ]
  • i.e., the offset is shifted to the left by 2, then sign extended.
bne $rs, $rt, LABEL
  • if ( Reg[ s ] != Reg[ t ] ) jump to LABEL else go to next instruction
  • I-type instruction
  • B31-26 = 000101
  • offset is B15-0
  • Jump to PC + [ (offset15)14 || offset || 02 ]
  • i.e., the offset is shifted to the left by 2, then sign extended.
slt $rd, $rs, $rt
  • if ( Reg[ s ] < Reg[ t ] ) Reg[ d ] = 0311 else Reg[ d ] = 032
  • R-type instruction
  • B31-26 = 000000 (SPECIAL)
  • B10-6 = 000000
  • B5-0 = 101010 (SLT)
slti $rt, $rs, immed
  • if ( Reg[ s ] < (immed15)16 || immed15-0) Reg[ d ] = 0311 else Reg[ d ] = 032
  • I-type instruction
  • B31-26 = 001010
jr $rs
  • R-type instruction (sort of)
  • B31-26 = 000000 (SPECIAL)
  • B20-6 = 000 0000 0000 0000
  • B5-0 = 000100 (JR)
j LABEL
  • PC <- PC31-28 || immed || 02
  • immed is 26 bit value
  • J-type instruction
  • B31-26 = 000010
jal LABEL
  • PC <- PC31-28 || immed || 02
  • immed is 26 bit value
  • Reg[ 31 ] <- PC + 4 (In the real MIPS, it should be PC + 8, but that's mostly because of pipelining--we use the simpler PC + 4, which is the next instruction).
  • J-type instruction
  • B31-26 = 000011
lw $rt, offset($rs)
  • I-type instruction
  • offset is sign-extended to 32 bits, and added to Reg[ s ] to produce address. The content of that address (which must be word-aligned), is placed in Reg[ t ]
  • B31-26 = 100011
  • B15-0 is the offset
lbu $rt, offset($rs)
  • I-type instruction
  • offset is sign-extended to 32 bits, and added to Reg[ s ] to produce address. The content of that address (which does NOT have to be word-aligned), is placed in Reg[ d ]
  • B31-26 = 100100 (CORRECTED)
  • B15-0 is the offset
sw $rt, offset($rs)
  • I-type instruction
  • offset is sign-extended to 32 bits, and added to Reg[ s ] to produce address. The content of Reg[ t ] is saved at that address (which must be word-aligned)
  • B31-26 = 101011
  • B15-0 is the offset
sb $rt, offset($rs)
  • I-type instruction
  • offset is sign-extended to 32 bits, and added to Reg[ s ] to produce address. The content of Reg[ t ] is saved at that address (which does NOT have to be word-aligned)
  • B31-26 = 101000
  • B15-0 is the offset
lui $rt, immed
  • I-type instruction
  • Reg[ t ] = immed || 016
  • B31-26 = 001111
  • B25-21 = 00000 (normally where rs goes, but leave it all zeroes)
bgtz $rs, LABEL
  • I-type instruction
  • B31-26 = 000111
  • B20-16 = 00000
  • Let offset = B15-0
  • PC-relative addressing. Let target = (offset15)14 || offset || 02
  • PC <- PC + target
bgez $rs, LABEL
  • I-type instruction
  • B31-26 = 000001 (REGIMM)
  • B20-16 = 00001 (BGEZ)
  • Let offset = B15-0
  • PC-relative addressing. Let target = (offset15)14 || offset || 02
  • PC <- PC + target
bltz $rs, LABEL
  • I-type instruction
  • B31-26 = 000001 (REGIMM)
  • B20-16 = 00000 (BLTZ)
  • Let offset = B15-0
  • PC-relative addressing. Let target = (offset15)14 || offset || 02
  • PC <- PC + target
blez $rd, LABEL
  • I-type instruction
  • B31-26 = 000110
  • B20-16 = 00000
  • Let offset = B15-0
  • PC-relative addressing. Let target = (offset15)14 || offset || 02
  • PC <- PC + target
sll $rt, $rs, shift_amt
  • R-type instruction
  • Shift left logical
  • B10-6 is the shift amount (between 0-31)
  • B31-26 = 000000 (SPECIAL)
  • B5-0 = 000000 (SLL)
  • Shift a copy of Reg[ t ] left by shift_amt bits, inserting zeroes into the low order bits.
srl $rd, $rt, shift_amt
  • R-type instruction
  • Shift right logical
  • B10-6 is the shift amount (between 0-31)
  • B31-26 = 000000 (SPECIAL)
  • B5-0 = 000010 (SRL)
  • Shift a copy of Reg[ t ] right by shift_amt bits, inserting zeroes into the high order bits.
sllv $rd, $rs, $rt
(SPRING 2003)
  • R-type instruction
  • Shift left logical variable
  • B10-6 = 00000
  • B31-26 = 000000 (SPECIAL)
  • B5-0 = 000100 (SLLV)
  • Shift a copy of Reg[ t ] left by the amount stored in low 5 bits of Reg[ s ], placing shifted result in Reg[ d ].
srlv $rd, $rt
(SPRING 2003)
  • R-type instruction
  • Shift right logical variable
  • B10-6 = 00000
  • B31-26 = 000000 (SPECIAL)
  • B5-0 = 000110 (SRLV)
  • Shift a copy of Reg[ t ] right by the amount stored in low 5 bits of Reg[ s ], placing shifted result in Reg[ d ].

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Last Modified: Wed Jun 5 10:38:37 EDT 2002
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