All problems are from Hennessy and Patterson, unless otherwise stated.
Hand in hard copy in class on the due date. Answers will be posted after
the due date.
Homework #1 - Unit 1 - Problems 1.2 (a-e), 1.7 (a-c), 1.12, 1.17 (a-d) - due
Sept. 16
- For 1.2 (a), just a few points for drawing the graph is
enough. For instance, calculate the "Net speedup" for the values [0, 0.2
, 0.4 , 0.6 , 0.8 , 0.1] of "Percent vectorization" and connect
the points.
- For
1.7, use a variable, say CR, to represent the clock
rate for both the embedded and RISC processors, with both processors having
the same CR.
Homework #2 - Unit 2 - Problems 2.1 (a,b), 2.3 (a-d), 2.6 (a,b), 2.10 - due
Sept. 23
- For 2.3 (a,b), you don't have to write the ASCII characters for each byte.
Homework #3 - Unit 3 - Problems A.1 (a,b), A.7, A.11, and 1
more - due Oct. 9
Homework #4 - Unit 4 - Problems A.13, 3.1, 3.7, 3.8, 3.10, 3.19 - due Oct. 30
Homework #4b - Unit 4b - Problems 4.6, 4.8, 4.15, 4.18 - due Nov. 13
Homework #5 - Unit 5 - all problems are here, none from
book - due Dec. 9
Project - Basic pipelining simulator, with useful files
- due Dec. 10
And another example input program, with corresponding output
Test cases used for grading, with correct output
Homework #6 - Unit 6 - Problems 7.9, 7.10, 7.12 (a,c) - not handed in,
answers posted after Dec. 11