Introduction to Flip Flops: D and T

Introduction

The basic building blocks of combinational logic circuits are gates. In particular, AND, OR, and NOT gates (however, there are also, XOR, NAND, NOR, XNOR gates too).

The basic building blocks of sequential logic circuits are flip flops. Flip flops are devices that use a clock. Each flip flop can store one bit.

Here's how a flip flop looks:

Basically, a flip flop has two inputs. One input is a control input. For a D flip flop, the control input is labelled D. For a T flip flop, the control input is labelled T.

The other input is the clock. You can read about clock from the class notes on clock.

The clock input is usually drawn with a triangular input. These flip-flops are positive edge-triggered flip flops. This means that the flip flops can only change output values when the clock is at a positive edge. There are also negative edge triggered flip flops, which change on a negative edge, and level-triggered flip flops, that change only when the value is 1. We consider only positive edge-triggered flip flops.

When the clock is not at a positive edge, then the output value is held. That is, it does not change.

A flip flop also has two outputs, Q and Q'. The output is really the bit that's stored. Thus, the flip flop is always outputting the one bit of information.

But you might wonder "Doesn't it have two bits of information? Q and Q'?". If you have two bits, you have four possible values. However, Q' is the negation of Q which means you only have two possible outputs: Q = 0, Q' = 1, Q = 1, Q' = 0. Since the second output is always negated from the first, you don't get any additional storage.

You might wonder why flip flops have two outputs, Q and Q'. It turns out you can design flip flops with NOR gates or NAND gates, with cycles (which is not allowed for combinational circuits). The design gives you Q' basically for free, so that's why flip flops have both the regular output and the negated output.

Although I rarely draw it, flip flops often have one additional input called asynchronous clear. It's drawn at the top of the flip flop. This is an active low asynchronous clear. "Asynchronous" means "without a clock" (usually). Active low, means you need to set the value to 0, to make it active.

Thus, if you set the asynchronous clear to 0, it causes Q to be automatically set to 0. It does this, even if the clock has not reached a positive edge. That is, it sets Q to zero as fast as it can. The asynchronous clear is often used to reset flip flops to some initial value. Often, you see active low inputs because it consumes less power.

The flip flops have additional inputs you don't see (so do logic gates for that matter). Flip flops and logic gates are powered devices. They need an input for ground and usually 5 volts (although there are low voltage versions of the flip flops). However, they're not drawn because they don't affect how the flip flop behaves.

Characteristic Tables

The behavior of a flip flops can be described by a characteristic table which is basically a truth table.

D Flip Flop Characteristic Table

Here's the characteristic table for a D flip flop.
  D     Q     Q+     Operation  
0 0 0 Reset
0 1 0 Reset
1 0 1 Set
1 1 1 Set

The D flip flop characteristic table has 3 columns. The first column is the value of D, a control input. The second column is the current state, that is the current value being output by Q. The third column is the next state, that is, the value of Q at the next positive edge. It's labelled with Q and the superscript, + (the plus sign).

Sometimes, the current state is written as Q(t) which means the value of Q at the current time, t, and the next state is written as Q(t + 1) which means the value of Q at the next clock edge. However, I'll usually write it as Q+.

The characteristic table is unusual, because the second column isn't really an input, it's an output. The third column is really the same output, but just the output at a future time.

The D flip flop has two possible values. When D = 0, the flip flop does a reset. A reset means that the output, Q is set to 0. When D = 1, the flip flop does a set, which means the output Q is set to 1.

This is how you can picture the flip flop working. When the clock is not at a positive edge, the flip flop ignores D. However, at the positive edge, it reads in the value, D, and based on D, it updates the value of Q (and of course, Q').

There is some small amount of delay while it reads in the control input (from D) and the output.

In fact, the "D" in D flip flop stands for "delay". It basically means that the "D" value is not read immediately, but only at the next positive clock edge.

T Flip Flop Characteristic Table

Here's the characteristic table for a T flip flop.
  T     Q     Q+     Operation  
0 0 0 Hold
0 1 1 Hold
1 0 1 Toggle
1 1 0 Toggle

The T flip flop characteristic table has 3 columns. The first column is the value of T, a control input. The second column is the current state, that is the current value being output by Q. The third column is the next state, that is, the value of Q at the next positive edge. It's labelled with Q and the superscript, + (the plus sign).

The T flip flop has two possible values. When T = 0, the flip flop does a hold. A hold means that the output, Q is kept the same as it was before the clock edge. When T = 1, the flip flop does a toggle, which means the output Q is negated after the clock edge, compared to the value before the clock edge.

Thus, in a T flip flop, you can either maintain the current state's value for another cycle, or you can toggle the value (negate it) at the next clock edge.

Why isn't it XOR?

If you look carefully at a T flip flop characteristic table, it looks a lot like XOR. Why isn't it XOR?

Several reasons. First, XOR has two inputs, and one output. A T flip flop essentially has a control input and a control output. Second, the second column and the third column are really the same output, but at different points in time.

Finally, the flip flop uses a clock, and can only modify the output at positive clock edges. A gate updates the output as soon as it can (based on the gate's delay).

JK Flip Flop Characteristic Table

Here's the characteristic table for a JK flip flop.

  J     K     Q     Q+     Operation  
0 0 0 0 Hold
0 0 1 1 Hold
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set
1 1 0 1 Toggle
1 1 1 0 Toggle

Basically, a JK flip flop is a combination of a D and T flip flop (or more accurately, a D and T flip flop are a simplification of a JK flip flop).

A JK flip flop has two control inputs, J and K. When JK = 00, the flip flop holds. When JK = 01, the flip flop resets. When JK = 10, the flip flop sets. When JK = 11, the flip flop toggles.

Why have all four possible operations? Often, when you study computer hardware, especially in an electrical engineering class, you learn how to minimize the circuit, using Karnaugh maps or the Quine-McCluskey algorithm. You can do more minimization if you use JK flip flops instead of D or T flip flops.

However, for the most part, we'll ignore JK flip flops, because we don't intend to do much minimization. Thus, JK flip flops are only mentioned for completeness (i.e., just so you know they exist).

Storing Information

The biggest difference between a flip flop and a gate is that a flip flop can hold its value. Although the D (or T) input can change all it wants, the output doesn't change, except at positive edges.

Even though holding a value is something very simple, it makes it different from logic gates, and allows us to design circuits that have cycles in them (i.e., feedback).

Summary

A flip flop is a device that can store 1 bit of information. There are three kinds of flip flops: D, T, and JK. We have ignored the JK flip flop, mostly because they're somewhat complicated. However, they are mentioned because they do exist.

A flip flop is a clocked device, which can change its value only at positive clock edges. When the clock is not at a positive edge, the flip flop maintains (holds) its value.

Flip flops allow sequential circuits to have state (i.e., memory), which is something that combinational logic circuits do not have.