| Lecture |
Date |
Topic |
| 1 |
6.02.03 |
- Introduction
- Fetch, Decode, Execute
- Bits, Bytes
|
|
| 2 |
6.03.03 |
- Data Representation: Bits, Bytes, and Nybbles
- Data Representation: Overview of Data Representation
- Data Representation: Converting from Base K to Base 10
- Data Representation: Converting from Base 10 to Base K
- Baby Circuits: Clock
- Baby Circuits: Wire
- Baby Circuits: Black Box
|
|
| 3 |
6.04.03 |
- Baby Circuits: Clock
- Baby Circuits: Wire
- Baby Circuits: Black Box
- Baby Circuits: MUX
- Baby Circuits: Register
|
|
| 4 |
6.05.03 |
- Baby Circuits: MUX
- Baby Circuits: Register
- Common Computer Sense: KMGTP
- Baby Circuits: Memory
- Data Representation: Big and Little Endian
|
|
| 5 |
6.06.03 |
- Data Representation: Overview of Signed Integers
- Data Representation: Signed Integers: Signed Magnitude
- Data Representation: Signed Integers: One's Complement (on your own)
- Data Representation: Signed Integers: Two's Complement (on your own)
- Data Representation: Signed Integers: Excess/Bias Represenationa
- Data Representation: Floating Point
|
|
| Lecture |
Date |
Topic |
| 1 |
6.09.03 |
- High level MUX
- Endianness
- Converting Decimal Fractions to base 10
- Fixed Point Notation
- Excess/Bias Notation
- Introduction to IEEE 754 Floating Point
|
|
| 2 |
6.10.03 |
- Scientific Notation
- Precision vs. Accuracy
- IEEE 754: Denormalized Numbers
- IEEE 754: Why Excess Notation For Exponents?
- IEEE 754: How Many Normalized Numbers? Denormalized?
- IEEE 754: Why -126 for Denormalized?
- Overview of One's and Two's Complement
|
|
| 3 |
6.11.03 |
- Defining Overflow
- Word Alignment
- Zero and Sign Extension
- Binary Coded Decimal
- Binary vs. ASCII files
- Summarizing Integer Representations: Values of 000 through 111
in all representations (UB, SM, 1C, 2C)
- Low-level C Programming: Bitwise/Bitshift Operators
|
|
| 4 |
6.12.03 |
- Introduction to MIPS
- RISC vs. CISC
- Translating Simple Arithmetic C Expressions
- Translating Conditional Statements
- Quiz on Number Representation
|
|
| 5 |
6.13.03 |
- MIPS Instruction Formats: R-type, I-type, J-type
- MIPS Pseudoinstructions: bge, bgt, ble, blt, li, la
- Translating Loops in C to MIPS
- RISC and Load/Store Architecture
- Load and Store in MIPS
- Manipulating 1D arrays in MIPS
- Loading 32 bit constants
- Fetch, Decode, Execute: How a Single Instruction Executes
|
|
| Lecture |
Date |
Topic |
| 1 |
6.16.03 |
- Exam 1 Given in Class:
- Low Level C Programming
- MIPS Assembly Language
- Challenge Section
|
|
| 2 |
6.17.03 |
- Putting a CPU together (Register Files, etc)
- Reviewing Exam Question: Clearing Range of Bits
- Reviewing Exam Question: Swapping Endianness
- RAM, in more detail. Various pin outs
|
|
| 3 |
6.18.03 |
- Putting a CPU together (Register Files, etc)
- Overview of ALU
- Adding a Sixth Step to Fetch, Decode: Updating PC
- Two Models of a CPU
- Detailed Fetching (Protocol from CPU to Memory)
- Endianness, Word Alignment for MIPS instructions
- Alternate Register Names in MIPS
|
|
| 4 |
6.19.03 |
- jal and jr in MIPS
- Caller vs. Callee
- Using the Stack in Function Calls
- Writing a Simple Function in MIPS
|
|
| 5 |
6.20.03 |
- Writing a Simple Recursive Function in MIPS
- Leaf Procedures
- Saving Registers to a Stack
- Functions
- Boolean Functions
- Boolean Expressions
- Truth Tables
|
|
| Lecture |
Date |
Topic |
| 1 |
6.23.03 |
- MIPS Addressing Modes: Register, PC-relative, Pseudodirect, Base
- Notation for Boolean Expressions
- Implementing Truth Tables: Minterms
- Logic Gates: NOT, AND2, OR2,
NAND2, NOR2, XOR2, XNOR2,
- Gate delay
- Implement a k-input AND gate using 2-input AND gates, minimizing
gate delay
|
|
| 2 |
6.24.03 |
- Revised MIPS CPU handout (Can now handle I-type)
- Functional Completeness of AND, NOT
- Functional Completeness of OR, NOT
- Functional Completeness of NAND
- Functional Completeness of NOR
- Implementing a 2-1 MUX using a truth table
- Implementing a 2-1 MUX using a condensed truth table
- Implementing a 4-1 MUX using a condensed truth table
- Implementing a 1-2 DeMUX using a condensed truth table
- Implementing a Half Adder
- Implementing a Full Adder
- Implementing a Ripple Carry Adder
- Delay of a Ripple Carry Adder
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|
| 3 |
6.25.03 |
|
| 4 |
6.26.03 |
|
| 5 |
6.27.03 |
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