We're going to build a very simple counter using T flip flops.
This counter is called asynchronous because not all flip flops are hooked to the same clock.
We can observe the behavior of the output of a T flip flop by looking at a timing diagram.
The output of the T flip flop (i.e., Q) can only change during positive edges. The positive edges are shown by vertical dashed lines.
Look at the waveform of the output, Q, in the timing diagram. It resembles a clock as well. If the period of the clock is T, then what is the period of Q, the output of the flip flop? It's 2T!
Thus, we have a very easy way to create a clock that runs twice as slow. We feed the clock into a T flip flop, where T is hardwired to 1. The output will be a clock who's period is twice as long.
So imagine we take the output of this T flip flop, that has a period of 2T, and feed this as the clock of another T flip flop, which also has its T input hardwired to 1. What would the period of that clock be?
Looking at the diagram above, the clock has period T. Q0 has period 2T. What period does Q1 have? It would be 4T! After all, that's what a T flip flop hardwired to 1 does.
It creates a clock that has twice the period. Since we fed in a clock with period 2T (the output of the first T flip flop), the output of the second flip flop has period 4T.
If we keep feeding the output of one T flip flop, into the clock input of another T flip flop hardwired to 1, and we do this for N flip flops, then what is the period of the output of the last flip flop? It's 2NT. Each flip flop doubles the period, so N flip flops is 2 raised to the Nth power.
We'll see why clocks that run twice as slow help us build a counter.
Look at the column labelled x0. It reads 0, 1, 0, 1, 0, 1, etc. If this were drawn as a timing diagram, it would look like a clock. Assume that this clock has period T.
Now look at the column labelled x1. It reads 0, 0, 1, 1, 0, 0, 1, 1. It looks like a clock too! However, it stays 0 twice as long, then 1 twice as long. In fact, it looks like a clock that has a period of 2T.
Now look at the column labelled x2. It reads 0, 0, 0, 0, 1, 1, 1, 1. Again, this looks like a clock, except it's going twice as slow! It has a period of 4T!
Does that sound familiar? It looks like the chained T flip flops we had above!
However, there is a difference. See if you can tell what that difference is.
If you were to draw the timing diagram for the two T flip flops drawn above, you would see that Q1 toggles on the positive edge of Q0. That makes sense, right? After all, we did feed Q0 into the clock of the next T flip flop, so Q1 should change only on Q0's positive edge.
However, that's not what's happening in the table above where we count from 000 to 111. In particular, notice when x1 changes from 0 to 1, or from 1 to 0.
For example, look at row 1 and row 2. In that row, column x1 has value 0, then value 1. What's happening in the same rows but in column x0? In that column, we see the value going from 1 to 0.
Thus, when x0 goes from 1 to 0, then x1 toggles. Either it goes from 0 to 1 (as in rows 1 to 2) or from 1 to 0 (as in rows 3 to 4).
This makes sense. Think about a regular odometer. You stare at it going from 008, to 009. Just when 9 is about to go to 0, the next column increments. Thus, you have 010. Thus, in a decimal odometer, the transition of digit i from 9 to 0 causes digit i + 1 to increment by 1.
For a binary odometer, that means that incrementing from 1 to 0 in bit i causes bit i + 1 to increment (equivalently, to toggle).
If we look at the T flip flops, we really want Q1 to toggle on negative edges of Q0. However, T flip flops toggle on positive edges. How can we solve this problem? To toggle on negative edges of Q0 is equivalent to toggling on the positive edges of Q0', which is the negation of Q0.
The following is a diagram of a 3 bit counter, using T flip flops.
And this is the timing diagram that shows how the counter behaves.
What's going on in this timing diagram? First look at the row that says CLK. That's the clock.
Then look at row X0. This toggles between 0 and 1 on the positive edge of the clock. That's because the clock is fed into the bottommost T flip flop.
X1 toggles on the negative edge of X0. That's because we feed X0' into the clock of the middle T flip flop (shown above).
X2 toggles on the negative edge of X1. That's because we feed X1' into the clock of the top T flip flop (shown above).
Does this create a counter?
Start reading the timing diagram. If you read it from the left most column, you see 000, then 001, then 010, then 011, and so forth. As you can see the output of the flip flops is incrementing as it should. The counter increments at a period of 2T, assuming the clock is has a period of T.
Second, if you count in UB from 000 to 111 (or in general, from k 0's to k 1's), then if x0 acts like a clock of period T, then xi acts like a clock of period 2iT. That is, each success column to the left is a clock that doubles the period.
Thus, we can combine these two facts together to generate a counter. Notice that the counter must increment based on negative edges. Thus, Xi+1 toggles on Xi. This is accomplished by feeding the negative output of a T flip flop (i.e. Q') to the clock of the next T flip flop.
This counter is considered asynchronous, since each flip flop runs on its own clock. Usually asynchronous has one of two meanings. Either it means a circuit that does not use a clock at all, or it means a circuit where all flip flops are NOT hooked up to the same clock (however, sometimes you have circuits with two clocks, and those are considered synchronous, as long as the two clocks have the same period---usually, this means part of the circuit runs on a positive edge, and the rest on a negative edge).