The principal goal of the authors in this chapter seems to be to justify the choices made in encoding the MIPS ISA. Thus, a brief overview of the history of computers is provided, from the viewpoint of the number of operands needed by an ALU instruction under a variety of architectural assumptions. For each of what I look at as the important sub-topics in the section, I've included the figure that i normallly use when going over them. Classification of ISA (Instruction Set Architectures) Stack: both operands known to be on stack; thus, ALU instruction requires no further operands. ACC: on operand known to be in accumulator already; thus APU instruction requires a single operand. GPR: general purpose register machines (all modern machines) (m,n) architectures or ISA's m is MAX number of memory references in ALU instruction n is REQUIRED number of operands in ALU instruction Note that RISC is (0,3). The MIPS language used by the book is (0,3). The P4 is an (1,2) ---- posted on newsgroup) note: looking at page 92, figure 2.1 is useful in understanding the relationship between the CPU and memory--whether or not an ALU instruction can have an operand that is a memory location, meaning that the address of the operand is not known until the instruction is decoded!!! figs 2.3, 2.4 provide details regarding GPR machines Memory organization Big Endian vs Little Endian (nice description p 96; alternative folllows) Memory organization based on the position in which the bytes of a multi-byte word are ordered when the word is stored in (byte-addressable) memory. We define the Most Significant Byte (MSB) to be the byte of a word that contains the most significant bit, also called the sign bit, or the bit corresponding to the coefficient of the highest power of two when the word is interpreted as an unsigned binary fixed point number. Similarly, the Least Significant Byte (LSB) is the byte that contains the least significant bit, or the bit that is the coefficient of two to the zero power of the corresponding unsigned binary number. Now, if memory is byte addressable, a 64 bit word would occupy consecutiveaddresses from 0 to 7, and would be loaded from addresses that were zero mod 8. Thus, I could load a 64 bitword from address 128, since 128 = 0 mod 8, but not from address 133, which is 5 mod 8. (See discussion of byte alignment below) Big Endian means that the MSB of a word is stored in the lowest address byte associated with that word. That is, the byte address of the MSB is 0 mod 4, and that is the address from which the word is loaded. Literally, it means put the"BIG END IN" first. (note that the LSB will be at an address which is 7 mod 8 if you are using 64 bit words) Little Endian refers to the opposite memory organization, where the "lttle end" or the LSB resides at the byte with the lowest address associated with the memory, for example, at 0 mod 8. Again, literally, you put the "LITTLE END IN" first. Note: if you don't mention memory addresses defining Big/Little Endian, don't expect even pity points. hammering on the time taken to access memory is useful for later---that is, to differentiate among the various potential access times (reference page 390 as needed---cpu-cache-memory-i/o picture) memory access times, in increasing order: 1) hit in L1 cache 2) miss in L1, hit in L2 cache 3) misses in L1 and L2, hit in L3 cache 4) misses in cache, hit in Main Memory (ram) 5) page fault---misses in cache and main memory (more about memory in chapter 5, and in tutorials) Byte Alignment issues----why does alignment matter; why aren't a addresses fair game for memory access.? 1) it costs money to have wires in memory to make all possible 8-bit or 16-bit or 32-bit chunks accessable. 2) Typical memories are organized by bytes, and individual bytes can be extracted. However, in memory hierarchies, RAM is transferred to cache in blocks, and bus bandwidth often determines how much information actually is transmitted between cache and RAM, or RAM and peripherals during any given transaction.. 3) Individual byte or half-word loads can be accomplished by downloading the word or doubleword containing the desired piece of data and then extracting the desired part and padding with zeros as specified by the ISA load. 4 Non-aligned access, when supported, require multiple aligned accesses. Note: Figure 2.5 on page 97 allegedly shows how alignment works; read it with the definition in front of you several times. Register Addressing modes: Figure 2.6 on page 98 shows how registers and extra symbols are used to access memory locations and to support programming constructs such as lists and auto increment and decrement. point out that MIPS only supports addressing of the form LW R2, 10(R1) That is, R2 will be getting the value stored at the memory location determined by computing the effective address (adding 10 to the value stored in register R1) of the desired operand. Basic Instruction Types: the bulk of the book assumes that we partition the functionality of instructions into three sets: ALU (INT, Logic and FP, unless otherwise stated) Memory Access (loads and stores) Control (not just branches--any instruction that can modify the PC when executed. FIgure 2.15 shows a more detailed list, and the text mentions distributed signal processing (DSP) architectures as well as MultiMedia architectures as requiring more application-specific instruction types and word sizes. Figure 2.17 shows a list of the different wordsizes used for multimedia applications on several different architectures. The rest of the chapter contains the MIPS language, which will be used for the remainder of the book/cour Knowing the mapping from different instructions to I-type, R-type, and J-type is useful, as is how each of these is processed. See the handout on the MIPs architecture on the webpage for more details. You need not memorize the MIPS architecture (i'll hand out the inside back cover of the book for exams, NOT quizzes.)