Unit | Latency | Initiation Interval | |
INT ALU | 0 | 1 | |
FP ADD | 7 | 1 | |
FP MULT | 17 | 1 | |
FP DIV | 59 | 66 (not pipelined!) |
For example, the value 0 corresponds to the latency between an INT ALU instruction producing a result that another INT ALU instruction needs. Each correct value is worth (1) point.
Hint: for each dependent instruction pair, identify which stage of the producer instruction is the ``source'' of the value that must be ``received'' by the consumer instruction.
Producer | Consumer | Latency |
Instruction | Instruction | |
INT ALU | INT ALU | 0 |
INT ALU | INT LOAD | 0 |
INT ALU | BNEZ | 1 |
INT Load | INT ALU | 1 |
FP ADD | FP ALU | 7 |
FP MUL | FP ALU | 17 |
FP Load | FP ALU | 1 |
The tricky one is the one with the BNEZ in it.
DADD R5, R5, R5 F D X M W
BNEZ R5, dump F S D X M W
That is, a FP ALU instruction has no use for a result from an INT ALU instruction; so, the latency is zero because they are independent. Similarly, an instruction that stores a value has no output! So, the latency of any instruction following it is always zero, because it is impossible for the first instruction to affect the values in the 2nd.
Producer | Consumer | Latency |
Instruction | Instruction | |
INT ALU | INT Store | 0 |
INT ALU | FP Load | 0 |
INT ALU | FP Store | 0 |
INT ALU | FP ALU | 0 (Independent) |
FP ALU | INT ALU | 0 |
FP ALU | FP Load | (# FP unit stages - 1) |
FP ALU | FP Store | (# FP unit stages - 2) |
FP Load | FP ALU | 1 |
FP Store | FP ALU | 0 (Independent) |