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Problem 1: Delayed Principles (25 points)

1.1
Fill in the following table regarding the latencies and initiation intervals of each functional unit. Each correct value is worth one point.

Unit Latency Initiation Interval  
INT ALU 0 1  
FP ADD 7 1  
FP MULT 17 1  
FP DIV 59 66 (not pipelined!)  



1.2
Using the information in the FU table and the pipeline structure, determine the latencies in the MMM-MIPS for potentially dependent pairs of ALU instructions in the table below.

For example, the value 0 corresponds to the latency between an INT ALU instruction producing a result that another INT ALU instruction needs. Each correct value is worth (1) point.


Hint: for each dependent instruction pair, identify which stage of the producer instruction is the ``source'' of the value that must be ``received'' by the consumer instruction.



Producer Consumer Latency
Instruction Instruction  
INT ALU INT ALU 0
INT ALU INT LOAD 0
INT ALU BNEZ 1
INT Load INT ALU 1
FP ADD FP ALU 7
FP MUL FP ALU 17
FP Load FP ALU 1

Instruction Latency Table

Answer:
To see where the numbers in the instruction latency table came from, write down two instructions that satisfy the consumer/producer roles above. Then, track their execution on the pipelike pipe, under the assumptions above, and determine how many stalls are required to clear the data hazard.

The tricky one is the one with the BNEZ in it.

DADD R5, R5, R5 F D X M W
BNEZ R5, dump F S D X M W

1.3
Answer: As in the previous problem, you needed to determine the latencies associated with the pairs of operations given below. To verify these, write out two instructions satisfying the producer/consumer instruction definition and count the stalls needed to have the data hazard clear. Notice that it's impossible to have to related instructions of the types noted as independent below.

That is, a FP ALU instruction has no use for a result from an INT ALU instruction; so, the latency is zero because they are independent. Similarly, an instruction that stores a value has no output! So, the latency of any instruction following it is always zero, because it is impossible for the first instruction to affect the values in the 2nd.

Producer Consumer Latency
Instruction Instruction  
INT ALU INT Store 0
INT ALU FP Load 0
INT ALU FP Store 0
INT ALU FP ALU 0 (Independent)
FP ALU INT ALU 0
FP ALU FP Load (# FP unit stages - 1)
FP ALU FP Store (# FP unit stages - 2)
FP Load FP ALU 1
FP Store FP ALU 0 (Independent)

Instruction Latency Table for Problem 1.3


next up previous
Next: About this document ... Up: work4-ans Previous: work4-ans
MM Hugue 2002-12-09

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