Problem 2: Primary Processes

2.1

Explain how a (1,3) GPR instruction set architecture (ISA) differs from a (0,3) GPR ISA.

2.2

Suppose your memory is byte addressable and Little Endian, with four (4) bytes per word and eight (8) bytes per double word. Write an expression for Z, the address from which I would load the most significant byte (MSB) of a double word.

That is, choose A and B such that any byte loaded from an address, $Z$, where

$$Z \;\equiv \; A \;{\rm mod}\; B$$

will be properly aligned, and will contain the most significant bit (msb) of the associated double word.

2.3

Write an expression for memory access time, given that the miss rate is 10% and the miss penalty is 500 times the hit time (HT).

2.4

Suppose that we consider a slightly different memory model. The miss penalty is still 500 times the hit time. However, separate memories are used for instructions and data. Furthermore,

• The miss rate for instructions is 7%,
• The miss rate for data is 13%.
• Loads transfer data from memory to registers, and make up 30% of the the instructions.
• Stores transfer data from registers to memory, and comprise 15% of the instructions.

Write an expression for the CPU execution time when the cache is not perfect.