| LD LD MULTD SUBD DIVD ADDD |
F6, 34(R2) R2, 45(R3) F0, F2, F4 F8, F6, F2 F10, F0, F6 F6, F8, F2 |
| Cycle | What happens |
| 1 | Issue LD F6, 34(R2); Mark integer unit BUSY LD F6 R2, Rj = yes Mark register result status F6/Integer |
| 2 | Read operands for LD F6, 34(R2); Cannot issue next instruction LD F2 45(R3) because integer unit is busy; STALL |
| 3 | Execute (completing execution in 1 cycle) for LD F6,
34(R2); Still stall on integer unit, cannot issue LD F2, 45(R3) |
| 4 | Write result for LD F6, 34(R2); integer unit goes free at
end of cycle Still stalled on integer unit; cannot issue LD F2, 45(R3) Clear F6/Integer from register restult status after this cycle |
| 5 | Issue LD F6, 34(R2);
Mark integer unit BUSY LD F2 R3, Rj = yes |
| 6 | Read operands for LD F6, 43(R2);
Issue MULTD F0, F2, F4; Mark MULT1 unit BUSY Mult F0 F2 F4, Qj = Integer, Rj = no, Rk = yes (Since Rj (F2) will be written by integer unit) Mark register result status F0/MULT1 |
| 7 | Execute LD F6, 34(R2); (completes)
Can't read operands for MULTD F0, F2, F4; stall waiting for integer unit to finish Issue SUBD F8, F6, F2 Mark Adder unit BUSY Sub F8 F6 F2, Qk = Integer, Rj = yes, Rk = no Mark register result status F8/ADD |
| 8 | Write result of LD F6, 34(R2); integer unit goes free at end of cycle
Clear F2/Ingeter from register result status after this cycle Can't read operands for MULTD F0, F2, F4; stall waiting for integer unit to finish Can't read operands for SUBD F8, F6, F2; stall waiting for integer unit to finish Issue DIVD F10, F0, F6 Mark DIV unit BUSY F10 F0 F6, Qj = MULT1, Rj = no, Rk = yes |
| 9 | Read operands for MULTD F0, F2, F4
Read operands for MULTD F8, F6, F2 Cannot read opearands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) |
| 10 | MULTD F0, F2, F5 executes (9 cycles after this)
SUBD F8, F6, F2 executes (1 cycle after this) Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot issue ADDD; must wait for SUBD to complete and free adder |
| 11 | MULTD F0, F2, F5 executes (8 cycles after this)
SUBD F8, F6, F2 executes (completes on this cycle) Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot issue ADDD; must wait for SUBD to complete and free adder |
| 12 | MULTD F0, F2, F5 executes (7 cycles after this)
Write result for SUBD F8, F6, F2; adder unit goes free at end of cycle Clear F8/Adder from register result status after this cycle Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot issue ADDD; must wait for SUBD to complete and free adder |
| 13 | MULTD F0, F2, F5 executes (6 cycles after this)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Issue ADDD F6, F8, F2 Mark Adder unit BUSY Add F6 F8 F2, Rj = yes, Rk = yes Mark register result status F6/ADD |
| 14 | MULTD F0, F2, F5 executes (5 cycles after this)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Read operands for ADDD F6, F8, F2 |
| 15 | MULTD F0, F2, F5 executes (4 cycles after this)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) ADDD F6, F8, F2 executes (1 cycle after this) |
| 16 | MULTD F0, F2, F5 executes (3 cycles after this)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) ADDD F6, F8, F2 executes (completes after this cycle) |
| 17 | MULTD F0, F2, F5 executes (2 cycles after this)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot write result for ADDD F6, F8, F2; WAR hazard on F6; must wait for DIVD to read operands |
| 18 | MULTD F0, F2, F5 executes (1 cycle after this)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot write result for ADDD F6, F8, F2; WAR hazard on F6; must wait for DIVD to read operands |
| 19 | MULTD F0, F2, F5 executes (completes after this cycle)
Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot write result for ADDD F6, F8, F2; WAR hazard on F6; must wait for DIVD to read operands |
| 20 | Write result for MULTD F0, F2, F5; MULT1 unit goes free at end of cycle
Clear F0/MULT1 from register result status after this cycle Cannot read operands for DIVD F10, F0, F6; stalled waiting for MULT1 to finish (needs F0) Cannot write result for ADDD F6, F8, F2; WAR hazard on F6; must wait for DIVD to read operands |
| 21 | Read operands for DIVD F10, F0, F6
Cannot write result for ADDD F6, F8, F2; WAR hazard on F6; must wait for DIVD to read operands |
| 22 | DIVD F10, F0, F6 executes (19 cycles after this)
Write result of ADDD F6, F8, F2; adder unit goes free at end of cycle Clear F6/ADD from register result status after this cycle |
| 23 | DIVD F10, F0, F6 executes (18 cycles after this) |
| 24 | DIVD F10, F0, F6 executes (17 cycles after this) |
| -- | |
| 41 | DIVD F10, F0, F6 executes (completes after this cycle) |
| 42 | Write result of DIVD F10, F0, F6; divide unit goes free at end of cycle
Clear F10/DIVD from register result status after this cycle |