1. The Crusoe is cheaper to manufacture because of its lowered transistor count. This is possible because of its Code Morphing software layer. This leads to decreased die sizes, and therefore allow for more cores to be manufactured from silicon wafers.

2. The Crusoe architecture allows for 64 or 128 bit instructions and allows for a maximum of 4 instructions per VLIW instruction.

3. There are several developments that led to the Crusoe. The first was the invention of trace scheduling in 1979. This allowed compilers to extract a sufficient amount of parallelism to be extracted from programs and keep the functional units on the processor busy. The second development was dynamic compilation, in the case of the Crusoe processor, Code Morphing. Dynamic compilation allows VLIW processors to perform the optimizations of dynamic scheduling, which is normally performed in hardware during runtime, in a software layer which executes during runtime and translates the code into it’s optimized form.

4. The Crusoe has processor specific techniques that allow for a cubic relation between power consumption and performance. Specifically, the Crusoe is able to dynamically alter the voltage and frequency based upon the current workload.

5. Memory is an issue for branch prediction because registers have to be mirrored to prevent data corruption.