Homework - due April *22* 1997

Problem 1

Assume that we have three scenarios - #1 is a fully associative cache, #2 is a two way set associative cache and #3 is a direct mapped cache. The cache size is 256 bytes. The cache line size is 8 bytes. All variables are 4 bytes. Assume that we have separate instruction and data caches. How many data cache read misses would we see from scenarios A) and B). State any assumptions that you make and justify your answer.

A:

  1. for(i=0;i<16;i++)
  2. {
  3. b += q*a[i];
  4. }

  5. for(i=0;i<16;i++)
  6. {
  7. c += r*a[i];
  8. }

B:

  1. for(i=0;i<16;i++)
  2. {
  3. b += q*a[64*i];
  4. }

  5. for(i=0;i<16;i++)
  6. {
  7. c += r*a[64*i];
  8. }

Hennessy and Patterson - Problem 5.1, parts A,B