Folks might be interested in the just released Volume 2 chapter 184.108.40.206 of
the Intel IA64 Architecture Software Developer's Manual It is the chapter on
IA64 MP Coherence and Synchronization. This document is now available from
It states the following, which is critical for ensuring publication safety
while not requiring strong loads.
Processor #0 Processor #1
st [x] = 1;; // M1 ld r1 = [y];; //M3
st.rel [y] = x // M2 ld r2 = [r1] //M4
Outcomes r1 = x and r2 = 0 is not allowed.
st and ld are weak stores and loads while st.rel is a store with release
semantics. The important thing to note is that ld.acq (load with acquire
semantics) is not required.
- Rick Hudson
Intel Microprocessor Research Lab.
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