>> As I mentioned previously, you can get this semantics by adding a
>> dummy volatile write before each volatile read, and a dummy volatile
>> read after each volatile write (so long as the dummy volatile is
>Does this mean that there is consensus that volatiles will have SC semantics
>between each other (vs. TSO)? I'd like to see SC, but I didn't know if there
I think we have consensus that TSO is too weak for volatile variables.
Hans Boehm and Rick Hudson have both expressed some concern that SC
might be to strong, and want to consider options that allow writes
from different processors to be seen in different orders on different
processors. Or something like that. See message below.
Hans and Rick: Time for you guys to put your argument together and
start making your case.
At 9:14 AM -0800 11/21/00, Hudson, Rick wrote:
>All processors will see writes made by a particular processor in the order
>written, aka processor order. If processor W writes a value and then updates
>the tail pointer then if processor R sees the updated tail pointer then
>processor R will see a legal value. In a two processor scenario where only
>one processor writes there is no interleaving so it is not interesting for
>our purposes here.
>In a two writer system (2 writers and n readers) the following interleavings
>can be observed.
>Write from processor 1 = W1
>Write from processor 2 = W2
>Tail Update from processor 1 = U1
>Tail Update from processor 2 = U2
>There are 6 possible interleavings, reading down.
>W1 W1 W1 W2 W2 W2
>W2 W2 U1 W1 W1 U2
>U1 U2 W2 U1 U2 W1
>U2 U1 U2 U2 U1 U1
>Even if we have 6 readers and each saw a different interleaving they would
>never read a bad value.
>- Rick Hudson
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