RE: JavaMemoryModel: Write atomicity for volatiles

From: Sarita Adve (
Date: Thu Jul 19 2001 - 15:09:01 EDT

To be complete, there are two other issues that are part of what I refer to
as write atomicity. I'll let Bill decide if we need to discuss them now or

Issue (A): Serialization of writes to the same location: Do writes to the
*same* location appear in the same order to all threads? That is, is the
following execution allowed?

Initially A=B=C=D=0
Thread 1
A = 1
B = 1

Thread 2
A = 2
C = 1

Thread 3
while (B! = 1) {;}
while (C != 1) {;}
register1 = A

Thread 4
while (B != 1) {;}
while (C != 1) {;}
register2 = A

Result: register1 = 1, register2 = 2

Note that there is a subtle difference between this and the option (3) I had

>> (3) A write can become visible to some other processors early.

Interpret "write becomes visible" as value of write is read by another
processor. Consider an update-based protocol for the above example where
both updates of A reach the caches of threads 3 and 4 before their reads,
but they reach them in a different order. Then option (3) isn't violated,
but the execution above is still allowed.

Issue (B): Termination of writes: Is a write eventually made visible to all

This is different from the infinite loop case we had earlier. You can view
the infinite loop question as whether a write will be issued (made visible
to *any* processor) at all? The above question is saying: if a write is
issued by a processor, will it be made visible to all processors?

I believe all commercial hardware cache coherence protocols today ensure
write termination and serialization. But from the above example, you can see
that with update protocols on NUMA systems, you'd have to do some special

On software DSM systems, the situation is different. Lazy release
consistency neither ensures write serialization nor write termination.


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