On Mon, 2 Dec 2002 11:26:50 -0500
Doug Lea <dl@cs.oswego.edu> wrote:
> Initially, a == null, x == 0
>
> Thread 1 Thread 2
> x = 1 r1 = a
> StoreStoreBarrier r2 = *r1
> a = &x
>
> Can r1 == a && r2 == 0?
>
> (Where StoreStoreBarrier is no-op on machines not needing them.)
>
> We'd like the answer to be no.
>
> We are pretty sure that this is so on some processors:
>[snip]
> * For alpha, section 5.6.1.7 of the Alpha manual includes indirection
> as an honored dependency (within processors).
I'm always reluctant to write anything about the Alpha memory model
when it is late at night (as it is here at the moment), but I don't
think 5.6.1.7 and a StoreStore is sufficient to prevent Thread 2 seeing
Thread 1's second write but not its first.
In this case "r1=a" precedes "r2=*r1" in Thread 2's depends relation,
but the depends relation is only used in defining the dependence
constraint in order to prevent causal loops; it does not in itself
constrain the order of the two reads in the main "BEFORE" relation.
I think Thread 2 needs a memory barrier too.
I'm not sure whether this flexibility is exploited by any existing
Alpha Architecture implementations,
Tim
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