Review Questions for Final
As the semester draws to a close, how much you got out of CMSC 311
is probably related to how much work you put into it. If you spent
very little time learning the material (i.e., didn't really read
lecture notes, or understand terminology) and practicing it, then
you may have found exams difficult.
If you attended classes, made sure you kept up, listened to hints
about the exam in class, then much of the exam should be do-able.
I often hint about things that might appear on the exam
or tell you it's on the exam (from exam 2, I told you there would
be a linking example, and to memorize the CPU diagram, and those
appeared on the exam).
For those of you taking CMSC 330 and CMSC 351, you realize that
good planning is necessary, and that studying even when there's
no exam is crucial because you can easily fall behind if you don't.
All of us fight time management issues. We know if we start
early, master the material covered in class as soon as possible,
we would do much much better. Few of us are immune to procrastination.
Well, that's the final soapbox.
Format
The exam should have the following structure. The exam should be
divided into six or seven parts. Each part should be about half the
length of either exam. The goal is to keep the exam as long as one of
the midterms (but you have 2 hours to work on it).
The exam may not be EXACTLY structured as below, but at least
you have an idea of the topics.
- Data Representation
- Low Level C programming
- MIPS programming (also, MIPS instruction format, how to compute addresses)
- Combinational logic
- Sequential logic (possibly timing diagrams)
- Memory (interleaved/cache)
- Challenge Section
I would like to put the following question on the final, so
be prepared for it.
Draw a register file for four parallel load registers. There
should be three busses, S1 bus, S2 bus (for source 1 and source 2
bus), and a DST bus (destination bus). Use tri-state buffers
and come up with the appropriate logic. This was done in
class, though I will post a solution for it.
Also, you might be asked, given the diagram on page 353 (or
some similar CPU), derive the diagram on page 360. Also, know
what the control signals are.
NEW: You do not have to memorize page 360. You do have
to know it well enough to figure out what the diagram means.
Review Questions
On to the review questions. Solutions may not necessarily
appear.
Cache
Look at the link to the Cache Quiz from the main webpage.
There's plenty of questions there. Here are some more.
- Why is word-alignment important for caches?
- Explain how caches use spatial locality.
- Explain how caches use temporal locality.
- How many bits for tag, given 128 slots, 32 bytes per slot,
using fully associative scheme? Using direct mapped?
- Assume 8 slots per set. Which bits of a 32 bit address
is used for what (tag, set number, offset)?
Interleaved Memory
- What is interleaved memory?
- Why do we use interleaved memory?
- Create the logic for a chip enable, assuming each RAM chip
stores 1K of memory.
- Draw a RAM chip with 1K of memory. What are the inputs?
What are the outputs?
Section 5.3 from book
- What are the control signals from the control unit?
- What parts of the CPU on page 360 use state (flip flops)?
- Which parts are combinational logic?
- What are the five steps to execute an instruction.
- Explain what parts of the CPU are used (and in what order)
for an add instruction.
- Explain what parts of the CPU are used (and in what order)
for a load instruction.
- Explain what parts of the CPU are used (and in what order)
for a brand instruction.
- How does the ALU indicate when a branch should or should
not occur?
- What's the difference between instruction and data memory?
- How do you think they're actually implemented (answer: instruction
and data cache)
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