| Datapath: performance | |||||||||||||
| Single-cycle performance | |||||||||||||
| Suppose operation times are: | |||||||||||||
| Memory: 2 nanoseconds | |||||||||||||
| ALU/adders: 2 ns | |||||||||||||
| Register file (read or write): 1 ns | |||||||||||||
| Assume MUXes, control units, PC access, sign-extend have no delay | |||||||||||||
| How long must the clock cycle be? | |||||||||||||