| MIPS: machine model | |||||||||||||
| Main memory | |||||||||||||
| data: 32-bit address: range from 0x00000000 to 0xFFFFFFFF | |||||||||||||
| upper half of range reserved (see fig. 3-22) | |||||||||||||
| Processor | |||||||||||||
| registers: store data to perform operations | |||||||||||||
| faster than main memory | |||||||||||||
| load-store architecture | |||||||||||||
| access memory only through load, store instructions | |||||||||||||
| load: register <--- data from memory | |||||||||||||
| store: register ---> data to memory | |||||||||||||
| amount of data in bytes (1, 2, 4, 8) depends on instruction | |||||||||||||
| all other operations use only registers or immediate values | |||||||||||||
| immediate: contained in instruction | |||||||||||||
| CISC: may use register and memory to perform operation | |||||||||||||
| 32-bit registers | |||||||||||||
| 32 general-purpose registers | |||||||||||||
| $r0-$r31 | |||||||||||||
| Design Principle #2: "Smaller is faster." | |||||||||||||
| 16 floating point registers | |||||||||||||
| ALU: arithmetic-logic unit | |||||||||||||
| performs operations on values in registers | |||||||||||||
| control: determines how operations executed ("computer within computer") | |||||||||||||