| Datapath: performance | |||||||||||||
| Single-cycle performance | |||||||||||||
| Suppose operation times are: | |||||||||||||
| Memory: 2 nanoseconds | |||||||||||||
| ALU/adders: 2 ns | |||||||||||||
| Register file (read or write): 1 ns | |||||||||||||
| Assume MUXes, control units, PC access, sign-extend have no delay | |||||||||||||
| How long must the clock cycle be? | |||||||||||||
| Instruction | Inst | Reg | ALU | Data | Reg | Total | |||||||
| type | mem | read | op | mem | write | ||||||||
| R-type | 2 | 1 | 2 | 0 | 1 | 6 | 0 | ||||||
| load | 2 | 1 | 2 | 2 | 1 | 8 | 0 | ||||||
| store | 2 | 1 | 2 | 2 | 0 | 7 | 0 | ||||||
| branch | 2 | 1 | 2 | 0 | 0 | 5 | 0 | ||||||
| jump | 2 | 0 | 0 | 0 | 0 | 2 | 0 | ||||||