| Multi-cycle datapath: memory read completion | |||||||||||||
| 5. Memory read completion | |||||||||||||
| Value read from memory is written back to register | |||||||||||||
| Reg[IR[20-16]] = MDR; | |||||||||||||
| Operation: | |||||||||||||
| Write the load data from MDR to target register $rt | |||||||||||||
| Control signals | |||||||||||||
| MemtoReg = 1: write from MDR | |||||||||||||
| RegWrite = 1: write the result register | |||||||||||||
| RegDst = 0: use $rt field from IR for result register | |||||||||||||