| Instructions: Data Transfer | ||||||||||||
| load and store architecture | ||||||||||||
| MIPS: can access memory only to transfer data to or from registers | ||||||||||||
| CISC: may allow, for example, add to memory location, store in register | ||||||||||||
| load: copy the data from memory into a register. | ||||||||||||
| store: copy the data from a register to memory. | ||||||||||||
| lw $rt, offset($rs) | Load word from memory location to register | |||||||||||
| sw $rt, offset($rs) | Store word from register to memory location | |||||||||||
| Offset is a 16-bit 2C value (immediate); all are I-type | ||||||||||||
| semantics of lw | ||||||||||||
| Addr <-- R[s] + (IR15)16::IR15-0 | ||||||||||||
| R[t] <-- M4[ Addr ] | ||||||||||||
| compute address | ||||||||||||
| - add the contents of register s (base) to the sign-extended offset | ||||||||||||
| - offset is immediate | ||||||||||||
| - non-aligned address: hardware exception | ||||||||||||
| get data | ||||||||||||
| - copy 4 bytes located at memory address starting at Addr to register t. | ||||||||||||
| - CPU fetches the four bytes based on the endianness of the machine | ||||||||||||
| sw similar to lw but the 4 byte quantity is copied from the register to memory. | ||||||||||||
| M4[ Addr ] <-- R[t] | stored in the endianness of the machine | |||||||||||