| Datapath: performance | |||||||||||||
| Single-cycle performance | |||||||||||||
| Suppose operation times are: | |||||||||||||
| Memory: 2 nanoseconds | |||||||||||||
| ALU/adders: 2 ns | |||||||||||||
| Register file (read or write): 1 ns | |||||||||||||
| Assume MUXes, control units, PC access, sign-extend have no delay | |||||||||||||
| How long must the clock cycle be? | |||||||||||||
| Instruction | Inst | Reg | ALU | Data | Reg | Total | Distribution | ||||||
| type | mem | read | op | mem | write | ||||||||
| R-type | 2 | 1 | 2 | 0 | 1 | 6 | 44% | 2.64 | |||||
| load | 2 | 1 | 2 | 2 | 1 | 8 | 24% | 1.92 | |||||
| store | 2 | 1 | 2 | 2 | 0 | 7 | 12% | 0.84 | |||||
| branch | 2 | 1 | 2 | 0 | 0 | 5 | 18% | 0.9 | |||||
| jump | 2 | 0 | 0 | 0 | 0 | 2 | 2% | 0.04 | |||||
| With single-cycle, clock period must be 8 ns | 6.34 | ||||||||||||
| But, not all instructions are loads! Suppose distribution of instruction types shown. | |||||||||||||