| Multi-cycle datapath: memory access/ALU completion | |||||||||||||
| 4. Memory access or R-type instruction completion | |||||||||||||
| Load or store: accesses memory | |||||||||||||
| Arithmetic-logical operation writes result to register | |||||||||||||
| Memory reference | |||||||||||||
| MDR = Memory[ALUOut]; or | |||||||||||||
| Memory[ALUOut] = B; | |||||||||||||
| Operation: | |||||||||||||
| If operation is load, word from memory is put into MDR. | |||||||||||||
| If operation is store, memory location is written with value from register B. | |||||||||||||
| (Where does memory address come from? | |||||||||||||
| It was computed by ALU in previous cycle. | |||||||||||||
| Where does register B value come from? | |||||||||||||
| It was read from register file in step 3 and also in step 2.) | |||||||||||||
| Control signals | |||||||||||||
| MemRead = 1 (load) or | |||||||||||||
| MemWrite = 1 (store) | |||||||||||||
| IorD = 1: address from ALU, not PC | |||||||||||||
| What about MDR? | |||||||||||||
| It's written on every clock cycle. | |||||||||||||
| Arithmetic-logical operation | |||||||||||||
| Reg[IR[15-11]] = ALUOut; | |||||||||||||
| Operation: | |||||||||||||
| ALUOut contents are stored in result register. | |||||||||||||
| Control signals | |||||||||||||
| RegDst = 1: use $rd field from IR for result register | |||||||||||||
| RegWrite = 1: write the result register | |||||||||||||
| MemtoReg = 0: write from ALUOut, not memory data | |||||||||||||