| Class | Chap | Comments | ||
| 1 | One | Intro, Survival Skills, Benchmarks | Units and Amdahl's Law | Start Ch. 1 HW |
| 2 | Dreaded CPU Equation | MIPS, MFLOPS and Machines | ||
| 3, 4 | Two | More Machine Details | ISA and Assembly Language | Start Ch. 2 HW |
| 5,6 | Three | Intro to DLX ISA | Intro DLX Pipeline | Start Ch. 3 HW |
| 7,8 | Pipeline Hazards: Data, Structural | Control Hazards | ||
| 9,10 | Multi-Cycle DLX | Loop Unrolling, Rescheduling | Start Ch. 4 HW | |
| 11 | Control Hazards | More Control Hazards | ||
| 12,13 | More Multi-Cycle DLX | and More | ||
| 14, 15 | Midterm: August 4, 2000 | |||
| 16,17 | Four | Scoreboard Algorithim | Tomasulo Algorithm | More Ch. 4 HW |
| 18,19 | Five | Other Instruction Level Parallelism | Memory Hierarchy Basics | Start Ch 5 HW |
| 20 | ||||
| 21,22 | Improving Memory Performance | Main and Virtual Memory | ||
| 23 | CPU and Memory CPI Effects | |||
| 24 | Seven | Networks | Start Ch 7 HW--TBD | |
| 25, 26 | Eight | Multiprocessors Models | Parallel Processor Models | HW TBD |
| 27, 28 | Overview and Loose Ends | Review | ||
| 29 | Final Exam August 24, 2000 |