MMX Technology Implementation

After setting the stage for frequency adn CPI performance, the instruction decode logic had to be modified to decode, schedule, and issue new instructions at a rate of 2 instructions per clock. With the two additional clock cycles per instruction. The pentium processor with MMX technology decode was redesigned to quadruple the throughput of OF instructions, allowing two instructions per cycle throughput.

MMX execution stage and MMX writeback stage were also been modified to improve performance of MMX ARITH-MEM instructions, the ARITH-MEM instruction is executed in a single clock cycle. According to the MMX technology archtecheture definition, the MMX register file is aliased to the FP mantissa register file. It was decided to design dedicated hardware to execute the MMX instructions. Teh unit has a MMX register file, capable of delivering four 64-bit operands and storing three 64-bit results in a single clock cycle. The MMX instructions also incorporates the MMX excution units, which were defined and designed as a module, and which allowed the disign to be shared with the Pentium II processor.