Different Architectures

1. Are modern CPUs Big Endian, Little Endian or Bi-Endian? Does it matter?

2. The new C Ansi Standard Library (ASL) requirements for Byte Ordering.

Take a look at the defition of big and little endian if you haven't already

Traditionally, CPU architectures have been designed to treat the bytes of words in memory as being arranged in big or little endian order, though there have been other architectures that used more exotic byte orders. This has been a long-lasting point of debate in computers, with both sides arguing that their ordering is the "correct" ordering and neither willing to seek common ground (though since the issue is the order of elements, it would be hard to define "common ground" at all).

Fortunately, the commercial market sometimes solves philosophical problems. For a variety of reasons (increased silicon budget, concern about future compatibility with Windows NT should it succeed commercially), as of around 1992 or so, most shipping commercial architectures are actually "bi-endian."

This means that the CPU is instructed at boot time to order memory as either big or little endian. Some CPU architectures, such as the the IBM/Motorola PowerPC architecture, which is derived from IBM's purely big-endian POWER RISC architecture, can also switch at runtime, but usually only with a very large performance impact. For practical purposes a "bi-endian" CPU runs either exclusively as big or little endian and provides switchability capability as a hedge against changes in the marketplace.

IBM added endian switchability in the PowerPC 601, the first of the PowerPC chips, to address compatibility concerns with Windows NT (Microsoft had previously announced that they had no plans to support Big Endian architectures, one way to solve the problem) and the aborted OS/2 for PowerPC project (originally called, "Workplace OS" the goal was to offer file format compatibility with the Intel x86 version of OS/2, which runs in little endian mode).

In the same time frame, the Sun Microsystems SPARC and Hewlett Packard PA RISC architectures also added boot-time endian-switchability

The Motorola MC68000 series (68000, 68008, 68010, 68020, 68030, 68040 and 68060) were all big endian, as is the RISCified variant of the 68000 line. Sun's SPARC chips are traditionally big endian and those that are switchable run Solaris in big-endian mode. Hewlett Packard's PA RISC architecture is another architecture that added switchability to the PA RISC CPUs used in the Gecko (HP 712) line of workstations. All Intel architecture chips (8088, 8086, 80186, 80286, 80386, 80486, Pentium, Pentium Pro, Pentium II) are strictly little endian, however to ease information exchange Intel added a byte-ordering instruction (BSWAP) to the 80486 and subsequent chips. The Dec Alpha is a little endian CPU, as are the MIPS/SGI CPUs.

Because big endian ordering has the most significant byte in the lowest address, while little endian has the most significant byte at the highest byte address, sharing information between different machines can be complicated. It is important to know the endian-ness of the machines so that the shared information will be correct. If you do not know the size of the data being transferred, or the endian-ness of the source and target machines, information that was sent may appear to be incorrect due to data conversions being done incorrectly.

This chart is available at http://www.ee.udel.edu/~vengroff/asl/lib/endiantypes.htm

With a be_int8 or a le_int8 we can only access one byte at a time and as the size of the bytes increase in size we must grab the same proportional size amount in order to assure proper byte alignment and the validity of the data.

Historical details on various CPUs are available at:

the Computer History archive

Great Microprocessors of the Past and Present

The CPU Info Center