Few terms are perhaps helpful to be defined before going to discuss SH-4 RISC processor.

Bus : A bus is a network topology or circuit arrangement in which all devices are attached to a line directly and all signals pass through each of the devices. Each device has a unique identity and can recognize those signals intended for it.

CPU : Central Processing Unit, mostly known as processors or microprocessors. This is where the calculations and computations take place.

Cache : A part of the memory system. This particular memory is located near CPU in order to bring the required data faster to the unit.

Hazards : The errors which can occur when using a pipeline architecture. This happens because the order of executing data can be switched because two or more instructions are being executed at the same time.

MIPS : Stands for Millions Instruction Per Second. A one of ways to measure the performance of the machine. In this case, it is measured how much instruction a machine can execute in a second.

MMU : Stands for Memory Management Unit.

Pipelining : The idea or concept of excecuting several instruction in the same clock cycle time. The idea which is used by RISC machines. Typical diagram of pipeline architecture can be seen by clicking here.

RISC : Stands for Reduced Instruction Set Computer; if you need to know more, go to the previous section, Introduction: The short description of RISC.

Sequential Execution : This is alternative to the pipeline execution. In this case instructions are executed in the order. No parallel executions occur.

Stalls : The common answer to handling the hazards caused by a pipeline architecture. Stalling basically put certain instructions on hold so that the proper data flow is maintained. Stalls are undesireable outcome, however, because it slows down the machine.

Superscalar : The architecture which relies on issueing a multiple instructions.

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