Assume The Position

A few standing assumptions about the DLX pipelines these loops are unrolled on: Both single and multicycle pipelines have separate instruction and data memories, use forwarding whenever possible, and have this little button that destroys the entire machine when you push it. For the multicycle pipeline, assume that the add and multiply FPFUs (floating point functional units) are fully pipelined (initiation interval = 1) and have 2 and 5 stages, respectively. (Note: I chose 5 stages to allow a little more flexibility with rescheduling.) I assume the DLX processor uses predict-taken branches and makes use of the branch delay slot. Compilers should (technically) add a NOP after the branch condition if the bds isn't being used. The branch instruction test occurs in the Execute phase.