We are considering carrying out a machine upgrade and we want to compare the performance we would obtain on some program that we frequently run. We are able to run the program on machine A, and conveniently enough, the program takes 100 seconds to run; 60 seconds are spent doing I/O and 40 seconds are spent computing. Possibly because this is a (sample) test question, we cannot run the program on machine B. Machine B has a processor/memory subsystem that is supposed to be 50% faster than machine A and an I/O subsystem that is supposed to be 30% faster than that of machine A. How much time should the program run on machine B?

Write code for the following in DLX: (DLX instructions from Figures 2.22 - 2.26 would be passed out with exam).

x += y[a[3]+10];

w = x*x;

Note: The base address of array a is stored in R10, the base address of array y is stored in R12. The address of x is stored in R14, and the address of y is stored in R16

Consider the following instructions:

LD F0, 0(R2)

MULTD F2,F0,F0

LD F4, 0(R3)

MULTD F6,F4,F4

LD F8, 0(R4)

MULTD F10,F8,F8

Assume the pipeline in Figure 3.44 of H&P (the figure would be supplied with exam), assume that instructions consume their operands at the beginning of their first execution cycle, and assume that MULTD has 7 execution stages (i.e. stages for MULTDare IF,ID, M1,M2,M3,M4,M5,M6,M7,MEM,WB).

1. Show the timing of these instructions with and without forwarding
2. Reorder the instructions to minimize stalls. How does the reordering affect the timing?

Give two examples from the following code of data dependencies, antidependencies, and output dependencies.

S1: LD F0,0(R1)

S2: ADDD F4,F0,F2

S3: ADDD F6,F0,F4

S4: LD F2,0(R3)

S5: SUBI R3,R3,#4

S6: MULT F6,F12,F2

S7: LD F2,0(R3)

Consider the following instructions:

S1: ADDD F0,F2,F4

S2: MULTD F2,F6,F8

S3: ADDD F8,F2,F4

I will provide you a description of what happens in Tomasulo’s algorithm on the first two cycles. Show what happens on the third cycle.

Registers:

Registers

Third Cycle: <FILL THIS IN YOURSELF>

Registers: