Doug Lea wrote:
>>If I understand your synopsis correctly, it will allow programmers to assume
>>that r2=1, r5=0 is not allowed. However, this outcome is allowed since there
>>is no inter-thread happens-before relationship here.
>>
>>
>
>Thanks! I forgot that you can't condense it so far as to avoid
>mentioning the fact that happens-before edges only occur when
>volatile reads and writes are to same variable. I'll add this.
>
This is true but not relevant to the current example. Even if you assume
that all volatile events must be totally ordered in the happens-before
relationship (irrespective of the variable they are directed at), you
can still get r2=1, r5=0. Here is the ordering:
r1=V2 --hb-> V3=1
With this, you still get that r2=B NOT--hb-> B=1, so the read of B can
see B=1, and of course r5 could be zero because of intialization.
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