All problems are from Hennessy and Patterson, unless otherwise stated.
Hand in hard copy in class on the due date. Answers will be posted after
the due date.
Homework #1 - Unit 1 - Problems 1.2 (a-e), 1.7 (a-c), 1.11, 1.17 (a-d) - due
Feb. 9
- For 1.2 (a), just a few points for drawing the graph is
enough. For instance, calculate the "Net speedup" for the values [0, 0.2
, 0.4 , 0.6 , 0.8 , 0.1] of "Percent vectorization" and connect
the points.
- For
1.7, use a variable, say CR, to represent the clock
rate for both the embedded and RISC processors, with both processors having
the same CR.
Homework #2 - Unit 2 - Problems 2.1 (a,b), 2.3 (a-d), 2.10, 2.12 (a,b) - due
Feb. 21
- For 2.3 (a,b), you don't have to write the ASCII characters for each
byte.
- For 2.12 (b), assume the addition of the new instruction doesn't change
the CPI
Homework #3 - Unit 3 - Problems A.1 (a,b), A.7, A.11, and
1
more - due March 7
Homework #4 - Unit 5 - not from the book - due March 31 -
answers
Project 1 - Basic pipelining simulator, with useful
files - due March 30, 6:00PM
And another example input program, with
corresponding output
Project 2 - Cache simulator, with useful
files - due April 27, 6:00PM
Homework #5 - Unit 4 - Problems A.13, 3.1, 3.7, 3.8, 3.10 - due May 2
Homework #6 - Unit 4b - Problems 4.6, 4.8, 4.18 - due May 4
Homework #7 - Unit 6 - Problems 7.9, 7.10, 7.12 (a,c) - not for hand-in