Example 1: CPU, Cache and Memory/Disk

This is the simplest architectectural model you will see. In this case, the miss penalty hides all the work below the cache level. So the memory access time ( ${\rm MAT}_{\rm ex1}$ ) is given by:

$${\rm MAT_{\rm ex1}} = {\rm HT} + {\rm MR} * {\rm MP}$$