You will be simulating the basic MIPS pipeline depicted in Figure A.18 of Hennessy & Patterson. We have provided pipeline register data structures specified in the file, mips-small-pipe.h. To enforce an implementation of your simulator that simulates pipelining, you are required to use these structures in their unmodified form. In other words, each cycle simulated by your simulator must produce the correct values for all the fields in the pipeline register data structures.
typedef struct IFIDStruct {
int instr;
int pcPlus1;
} IFID_t;
typedef struct IDEXStruct {
int instr;
int pcPlus1;
int readRegA;
int readRegB;
int offset;
} IDEX_t;
typedef struct EXMEMStruct {
int instr;
int aluResult;
int readRegB;
} EXMEM_t;
typedef struct MEMWBStruct {
int instr;
int writeData;
} MEMWB_t;
typedef struct WBENDStruct {
int instr;
int writeData;
} WBEND_t;
typedef struct stateStruct {
int pc;
int instrMem[MAXMEMORY];
int dataMem[MAXMEMORY];
int reg[NUMREGS];
int numMemory;
IFID_t IFID;
IDEX_t IDEX;
EXMEM_t EXMEM;
MEMWB_t MEMWB;
WBEND_t WBEND;
int cycles; /* number of cycles run so far */
} state_t, *Pstate;
There are three small modifications in the above pipeline register data structures as compared with Figure A.18 in Hennessy & Patterson. First, we don't latch the ``branch taken'' signal in the EXMEM register. Instead, when your simulator computes the direction of the branch in the execute stage, you can directly modify the PC register from the execute stage. Second, the MUX in the WB stage has been moved to the MEM stage. Therefore, the MEMWB pipeline registers only latch two values, instr and writeData, instead of three values as indicated by Figure A.18 in the text. Finally, we have added an extra pipeline register after the WB stage. Instead of communicating internally through the register file, your simulator will always forward from the pipeline registers. For instance, in Figure A.7 of the text, there is a communication path from the DADD instruction to the OR instruction internally through the register file (this is achieved by writing the register file on the first half of the clock cycle, and reading the register file on the second half of the clock cycle). In your simulator, this register communication will be replaced by forwarding between the WBEND pipeline registers to the execute stage of the OR instruction in cycle CC6.
As mentioned above, your simulator must produce all the values for the
pipeline register data structures on a cycle-by-cycle basis. In
addition, your simulator must also use the following simulator loop
code (which we have provided):
while (1) {
printState(state);
/* copy everything so all we have to do is make changes.
(this is primarily for the memory and reg arrays) */
memcpy(&new, state, sizeof(state_t));
new.cycles++;
/* --------------------- IF stage --------------------- */
/* --------------------- ID stage --------------------- */
/* --------------------- EX stage --------------------- */
/* --------------------- MEM stage --------------------- */
/* --------------------- WB stage --------------------- */
/* transfer new state into current state */
memcpy(state, &new, sizeof(state_t));
}
You will insert the necessary code between the comments that perform the functions at each pipeline stage, but do NOT need to change any other part of this loop. Especially, be careful not to change the output format of printState. Within each pipeline stage, the code will compute the new values of the pipeline register data structures (stored in the ``new'' structure) as a function of the old values (stored in the ``state'' structure). In other words, new should appear on the left-hand-side of your equations, and state should appear on the right-hand-side. Then, after the code in all the stages have computed their values, the ``memcpy'' at the end of the simulator loop copies the values from the new structure into the state structure. This corresponds to the rising edge of the clock latching values into the pipeline registers for the next clock cycle.