Your simulator should deal with data hazards by bypassing values from the pipeline register data structures. You can implement such data forwarding by checking for data dependences in the execute stage. For every instruction that enters the execute stage, you will have to check against the results produced by the previous 3 instructions (whose results can be found in the EXMEM, MEMWB, and WBEND pipeline registers). If there are no data dependences, then the execute stage should take its operands from the readRegA and readRegB IDEX pipeline registers. If there are data dependences, then the execute stage should instead copy the results from the pipeline register of the dependent instruction.
Most data hazards can be resolved using bypassing. However, there is one case that requires stalling the pipeline. If an instruction uses a source register that is the destination register of an immediately preceeding load instruction, then the pipeline must be stalled for a single cycle. This can be implemented by checking for such a dependence in the decode stage and inserting a bubble (NOP instruction - see Section 5.4.2) instead of allowing the instruction to proceed. One special case is when a load from a location is immediately followed by a store. The depending store can be bypassed by forwarding from the MEM/WB latch (loaded value) to the data memory write port of the memory stage (store instruction). However, for your implementation, you will not need to implement this; simply stall the pipeline one clock cycle for ALL load instructions that are followed by a depending instruction, even if the depending instruction is a store.