The pipeline you will be simulating will have a branch delay of 2 cycles since the branch direction is not resolved until the end of the execute stage. Instead of stalling the pipeline for 2 cycles after every fetched branch, your simulator should implement a ``hybrid'' static branch prediction scheme. In this scheme, you should predict taken for backward branches, and predict not-taken for forward branches. To implement this hybrid scheme, test the immediate value in the fetch stage on every fetched branch instruction. If the immediate value is positive, then fetch the next consecutive instruction on the following cycle. If the immediate value is negative, then fetch the branch target (computed as a PC-relative address using the offset) on the following cycle.
Make sure that your simulator validates the branch direction computed in the execute stage against the predicted direction. If the prediction was correct, no action should be taken. If the prediction was incorrect, then the simulator must squash the two instructions in the branch delay, which at this point will be in the IFID and IDEX pipeline registers. This squashing can be accomplished by replacing the incorrectly fetched instructions with NOP instructions and clearing all the other state in the IFID and IDEX pipeline registers.