From Alpha AXP Architecture reference manual, 2nd edition, by Richard
Sites and Richard Witek, Section 188.8.131.52, page (1) 5-17 (paraphrased):
The two columns show actions by processor Pi and processor Pj. A R(x,2) action
refers to reading location x and seeing the value 2. A W(y,2) action
refers to writing a 2 into location y. A MB action is a memory
barrier. All memory locations are assumed to start initialized 1.
Names such as [U1] are just names used to refer to actions.
[U1] W(x,2) [V1] R(y,2)
[U3] W(y,2) [V2] R(x,1)
There are no conflicts in this sequence. We can infer the following
partial order: V2 <= U1 <= U3 <= V1. There is not conflicting
implication that V1 <= V2.
OK. So that means that the Alpha MM specification doesn't easily
support fast and safe implementations of OO languages on SMP's (even
just limiting ourselves to the object header/vtbl; ignore the issue
of stale object fields for the memory).
Does anyone know about the actual implementations? The specifications
of memory models are often far more aggressive than the current
implementations, to allow future designs headroom.
Maybe we should try to bring some of the more senior architecture
people at Dec into this discussion. This could have serious
implementations for them.
As I mentioned before, I think the Sparc RMO MM is OK. I haven't
found anything yet in the Intel Merced spec that looks like a formal
I know the architecture people are very aggressive, and want to avoid
all constraints on their memory model. This issue of stale object
headers may just be the point where the PL people come in and say
"No, you shouldn't do that".
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