> As I mentioned before, I think the Sparc RMO MM is OK. I haven't
> found anything yet in the Intel Merced spec that looks like a formal
> memory model.
Have people looked at the "IA-64 Application Instruction Set
Architecture Guide, Revision 1.0"? Section 4.4.7 (page 4-18)
indicates quite clearly that IA-64 implements almost a pure release
consistency model. Most loads and stores are designated as unordered,
but some loads can be designated as "acquires" and some stores can be
designated as "releases". Here are some quotes:
"Memory data access ordering must satisfy read-after-write (RAW),
write-after-write (WAW), and write-after-read (WAR) data dependencies
to the same memory location. In addition, memory writes and flushes
must observe control dependencies. Except for these restrictions,
reads, writes, and flushes may occur in an order different from the
specified program order."
"Unordered data accesses may become visible in any order. Release data
accesses guarantee that all previous data accesses are made visible
prior to being made visible themselves. Acquire data accesses
guarantee that they are made visible prior to all subsequent data
I assume therefore that an IA-64 architect would say that a store of a
pointer to a newly constructed object should be a release-store
(st.rel) and the load of a pointer to a (potentially) newly
constructed object should be an acquire-read (ld.acq).
In addition, the PowerPC memory model is just as relaxed as the Alpha
model, and also allows reads to be reordered. However, I don't know
if any PowerPC implementations actually take advantage of that
possible reordering. The Alpha and PowerPC both have memory barrier
(fence) operations, but do not include explicit acquire/release memory
operations because the ISA designers did not want to waste opcode
Compaq Western Research Laboratory (a.k.a. DEC WRL)
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