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Tutorials Program - SIGMETRICS 2001 / Performance 2001

Modeling and Analyzing CPU Power and Performance: Metrics, Methods, and Abstractions

Margaret Martonosi
Princeton University

David Brooks
Princeton University

Pradip Bose
IBM Research

The power dissipated by current computer systems is an increasingly pressing problem. As mobile and handheld computers become ubiquitous in our society, extending the battery life of these battery-powered devices becomes a major design goal. Power efficiency also impacts the thermal design of computer systems. In desktop systems, the extreme amounts of power consumed by high-end microprocessors necessitate elaborate packaging and cooling techniques that add significantly to the cost of these systems. By the next generation of high-end processors, power dissipation is expected to be a major limiter on the design choices available to designers, and therefore a major limiter on the performance of next-generation CPUs.

Given the importance of the power problem, it is clear that developing solid power modeling techniques will become increasingly crucial to attack and understand the problem. The power modeling problem is a complex one. Even more so than performance, the best power models are quite low-level, relying on capacitance data from a chip that has already been fully designed. Increasingly, however, architects need basic feedback on power consumption as they make design decisions, much earlier in the process of architecting a system. Therefore, modeling techniques that abstract key aspects of power dissipation, while maintaining as much accuracy and speed as possible, are key to addressing this issue.

This tutorial will offer an introduction to power and performance modeling for computer design. We will discuss a range of modeling methods, from low-level methods based on capacitance estimates employed by CAD tools such as Synopsys PowerMill, to higher-level methods intended mainly for early-stage architecture-level power modeling. Finally, we will present strategies for determining and validating abstractions that can be useful in accelerating power modeling without dangerously degrading its fidelity . In addition to the lecture format, we will also give demonstrations of tools, measurements and validation techniques in action.

Who should attend?
The tutorial is primarily intended for an audience of computer architects, performance modelers and/or simulator builders who are interested in learning about modeling challenges and opportunities in the arena of power dissipation modeling. We also welcome the participation of other experienced power modelers who would like to engage in discussion about the pros and cons of various techniques.
Prof. Margaret Martonosi is currently an associate professor in the Princeton University Department of Electrical Engineering, where she has been on the faculty since 1994. Martonosi's research interests include computer architecture, the hardware/software interface, and related modeling/simulation issues. Her current work particularly focuses on power-efficient systems. Martonosi received her Ph.D. in Electrical Engineering from Stanford University in 1993. She also holds a master's degree from Stanford University and a Bachelor's degree with distinction from Cornell University, both in Electrical Engineering.

Dr. Pradip Bose is a research computer scientist at IBM T. J. Watson Research Center, Yorktown Heights, NY. He has been with IBM since 1983. Bose currently leads a research project at Watson on power-aware microprocessor design and modeling. His research interests include computer architecture, modeling and validation. Bose received his M.S. and Ph.D degrees in Electrical and Computer Engineering from University of Illinois, Urbana-Champaign in 1981 and 1983, respectively. He also holds a Bachelor's degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology (IIT), Kharagpur, India.

David Brooks is currently pursuing a Ph.D degree in Electrical Engineering at Princeton University. His research interests include architecture-level power-performance modeling and the definition of power-efficient, high-performan ce microarchitectures. He received his BSEE from the University of Southern California and his MA degree in Electrical Engineering from Princeton. By Summer, 2001, he is planning to be finished with his PhD and is planning to take a faculty position as of September, 2001.

[Last updated Mon Jan 1 2001]

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