Must be viewed w/ table-capable browser, such as Netscape

REVIEW SESSION: Sunday, May 18

in room 1112 at 7:00 PM.... But you don't care because this was, like, four years ago

Introductory lecture on Networking and Internet (by Jeff Hollingsworth)

Lecture on Address resolution, Routing

Solutions for 2nd Exam

Material Covered in 2nd Exam

Sketches of solutions to 1st three sample questions

Additional sample questions

Solution to Sample Virtual Memory Problem -- discussed Tuesday

Sample Virtual Memory Problem -- to be discussed Tuesday

Homework Solution for homework April 24

Homework due April 24 - NOTE: SECOND PROBLEM IS H&P 5.1, Parts a,b

Lecture Notes about Segmentation and Paging

Qu estions and Answers - (Please ignore questions 5 and 6 - they cover material that I'm not discussing in 411) NOT AVAILABLE

Class Hours: Tues & Thurs, 12:30pm to 1:45 pm,

Text: Computer Architecture: A Quantitative Approach, second edition, by John L. Hennessy and David A. Patterson, 1996, ISBN 1-55860-329-8. We will cover Chapter 1-7 of the text. Within the chapters I cover, I will dedicate more attention to some sections than others; as the course progresses, I will let you know which sections you should concentrate on.

Coursework: will consist of 6 homework assignments, two in-class exams and a final exam. Current class grades and averages will always be available at the bottom of this page. Please check all grades and tell us if there are any discrepancies. All work that you submit in this class must be your own; group efforts are considered academic dishonesty. Please read the statement on academic integrity.

Newsgroups: Either the TA or I will answer questions of general interest posted to the newsgroup csd.cmsc411. This newsgroup is currently unmoderated, and shared with the other section of 411. However, we will convert it to a moderated group or remove it altogether if it is used for other than constructive questions or comments. You may also be interested in comp.arch.

Appeals: If you feel that you have been graded unfairly, please discuss it with the TA first, then see me. Keep copies of all earlier work and tests.

Homework

There will be six homework assignments during the course of this semester, due in class on the assigned date. Graded homeworks will generally be returned one week later, and solutions will be posted to this web page.

Late homeworks will not be accepted, i.e. I will not accept any homeworks I receive after leaving the classroom. Students will be allowed to drop their lowest homework grade or to not turn in a homework assignment. .

Topics Covered

All numbers refer to Chapters in Hennessey and Patterson.

• Chapter 1: Amdahl's law, quantifying CPU performance, introduction to memory hierarchies, benchmarking - perils and pitfalls
• Chapter 2: Instruction sets, addressing modes, operations in instruction set, instructions for control flow, encoding an instruction set. Overview of compiler optimizations and relationship between compiler and computer architecture.
• Chapter 3: Introduction to the concept of pipelining. Pipeline hazards - data hazards, control hazards, structural hazards. Representation of pipelines. Stalls and methods for estimating pipeline performance. Methods of optimizing pipeline performance including forwarding and instruction scheduling. Approaches to dealing with pipeline problems posed by branches including Branch prediction and delayed branches. Issues raised by floating point operations. Examples - MIPS R4000 pipeline.
• Chapter 4: Instruction level parallelism,pipeline scheduling, loop unrolling. Dependencies - strategies for dealing with name, control and real data dependence. Out-of-order execution - dynamic scheduling with a scoreboard, the Tomasulo algorithm, branch prediction, branch target cache. Multiple issue pipelines. Compiler support for instruction level parallelism. Hardware support for extracting instruction level parallelism. Examples, study of PowerPC 620 plus examples drawn from other architectures. (I will supply information on these architectures via lecture and web pages).
• Chapter 5: Memory hierarchy design. How caches work. Mechanisms for reducing cache misses - block size, associativity, victim caches, hardware prefetching, compiler controlled prefetching, compiler optimizations. Cache design - approaches to reducing penalties for cache misses. Principals behind main memory design. Virtual memory - paging, segmentation. Examples of memory system design - Alpha and Pentium processors.
• Chapter 6: Storage systems. The importance of I/O. Types of storage devices. I/O busses. I/O processors. I/O performance measures. RAID. Design of I/O subsystem and relationship of I/O subsystem with the rest of a memory hierarchy. Example: UNIX file system performance, Compiler/runtime system directed I/O. Network attached peripherals. (I will supply additional information not in the text of many of these issues).

Grades

Final Grade: Homework: 30%, Each of two tests: 20%, Final Exam 30%.