Interal Workings of the UltraSparc IIi

The UltraSparc IIi is Sun Microsystems offering for the standards based V9 Sparc architecture. The chip provides a good base for networked servers because of its integrated CPU, PCI Bus and Memory controller. The architecture is also proven technology with the UltraSparc family of processors.

By providing low latency memory and bus interconnects on chip the UltraSparc IIi utilizes low cost PC-class PCI based parts instead of more expensive proprietary standards. Sun also incorporates a APB (Advanced PCI Bridge) to provide more independent PCI buses for higher performance systems. This is also supplemented by the Ultra Port Architecture (UPA) for accelerated graphics which is much like the Accelerated Graphics Port (AGP) found on many PC motherboards today.

The processor is available in a range of speeds: 270, 300, 333, 360, 440, and 480 MHz. It also allows for a Dual Processor System Controller (DPC) for inexpensive dual-processing systems.

This set of pages intends to give an overview over the UltraSparc IIi. This page was originally supposed to show the new designs of the UltraSparc III. But since Sun has only released very limited technical information on the UltraSparc III including no programers manual. Therefore this limits the information contained within to the older IIi processor.

Furthermore we will see how the UltraSparc IIi has encountered the same CPU design decisions that are disscussed and studied in Hennessy and Paterson. At the end of the presentation there will be questions that review the content that is discussed throughout the course of the web pages to extract the most important facets of the UltraSparc IIi design.