2.The UltraSparc has dynamic branch prediction, what way discussed in H&P is the choice for this processor?
3. The UltraSparc IIi has a Data Cache which is independent from the Instruction Cache, what memory write-back strategy is utilized in the Data Cache.
4. In H&P we find that Structural Hazards are easy to deal with name a way the UltraSparc IIi deals with a structural hazard.
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Answers:
1. It can issue up to 4 instructions but only 2 of them can be ALU instructions.
2. The dynamic branch prediction is by way of a 2bit predictor and branch prediction buffer.
3. It uses a write-through policy in which the process writes to the current level and the one below it.
4. It uses a 8-way register ports to allow multiple memory/register accesses at once.