RISC-Q

Modular quantum control

RISC-Q models a quantum control system through functional components: RF signal processors, controllers, custom accelerators, and communication modules.

Pulse-level programs, fully on chip

RISC-Q allows pulse-level programs written in RISC-V-compatible languages, such as C and Rust, to run fully on chip. This enables on-chip calibration, control, sensing, and learning protocols with feedback in existing high-level programming languages. A C library is provided, and a debugging and testing tool for on-chip protocol development is under development.

QICK, QubiC, and RISC-Q

The following table summarizes the comparison reported in the RISC-Q paper.

(a) Feedback latency is evaluated in the fast-reset task.
(b) Network latency is measured for one-way communication between two directly connected QCSoCs.
(c) Root-mean-square (RMS) jitter integrated from 10 Hz to 100 MHz at 6.5 GHz.

Scalable quantum error correction

A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency appeared at IEEE QCE 2026, part of IEEE Quantum Week. Built on RISC-Q, the system integrates quantum control, decoding, and feedback across multiple FPGA boards, connecting scalable control infrastructure with the real-time demands of quantum error correction.

A generator for real-time quantum control

RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V appeared at DAC 2026. RISC-Q brings modular hardware generation and RISC-V-compatible programming together to support customized quantum control systems and hardware–software co-design.

RISC-Q-based development with QubiC and QICK

In collaboration with the QubiC and QICK teams, we are working toward migrating these systems to RISC-Q-based development for future releases.

A generator for message-passing decoders

We are developing a generator for hardware-accelerated message-passing decoders for quantum error-correcting codes, extending RISC-Q's support for specialized error-correction hardware.

RISC-Q

A talk at the workshop Real-Time Fault-Tolerant Quantum Computing: Bridging Theory and Practice, part of IEEE Quantum Week 2026.

RISC-Q: A Brief Introduction

Invited talk · 50 minutes.

RISC-Q: A Brief Introduction

Invited talk · 45 minutes.

System-Level Design for Quantum Real-time Control and Error Correction

1. Real-Time Requirements for Controlling Quantum Systems
2. Quantum Error Correction–Related System Design
3. RISC-Q as a Generator for Quantum Control SoCs
4. Case Study: RISC-Q–Based Quantum Error Correction System
5. Case Study: RISC-Q–Enabled Hardware Acceleration Modules

RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V

If you use RISC-Q in your work, please cite our paper.

Junyi Liu, Yi Lee, Haowei Deng, Connor Clayton, Gengzhi Yang, and Xiaodi Wu.
DAC 2026.

@misc{liu2025riscqgeneratorrealtimequantum,
  title = {RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V},
  author = {Junyi Liu and Yi Lee and Haowei Deng and Connor Clayton and Gengzhi Yang and Xiaodi Wu},
  year = {2025},
  eprint = {2505.14902},
  archivePrefix = {arXiv},
  primaryClass = {cs.AR},
  url = {https://arxiv.org/abs/2505.14902}
}